As it is known by one skilled in the art, the data processing cores of integrated circuits (ICs) are generally surrounded with pads defining together an integrated pad ring. A pad is a cell which receives signals from outside the integrated circuit and drives them to the core through one of its input pins (or terminals) and/or drives the signals outputted by the core through one of its output pins (or terminals). So, the so-called “input pads” are each connected to at least one core input pin, the so-called “output pads” are each connected to at least one core output pin, and the so-called “bi-directional pads” are each connected to at least one core input and output pin as well as an output enable pin. A pad may also be arranged to adapt the voltage levels between the outside of the integrated circuit and the core which can work with different voltage levels.
In order that signals could be driven from the outside of an integrated circuit into its core, it is normally required that the core be powered up. In the same way, in order that signals could be driven from an integrated circuit core to the outside of this integrated circuit, it is normally required that the core be powered up.
When the core is not used by the system to which it belongs, it is useful to power down this core in order to minimise the system power consumption. But, it is difficult to power down a core without risking one of its output pins driving signals on the board, or another integrated input pin inducing an unknown state on it and, therefore, generating noise and/or power consumption issue. It is also difficult to power down a core without the risk of one of its input pins driving non-power logic signals in it which may induce core damages, such as reverse polarisation of transistor junctions.
Moreover, a major part of the pads, which are dedicated to normal functioning of the core, can also be dedicated to testing such as a Boundary Scan Test and also a scan test. In this case the pad configuration is not the same as the one established during normal functioning of the core. For example, a pure bidirectional pad can be forced into input or output mode during a test. Therefore, there are often paths to and from the test pads that cannot be crossed and tested.
The more the cores have different sizes, the more the paths between a core and its pads may vary, which can induce non desirable delays. This is notably the case when test paths are linked to functional paths.